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product specifications september 24, 2003 version 1.32 u ltra c hip the coolest lcd driver. ever!! 65com x 132seg matrix lcd controller-driver h igh -v oltage m ixed -s ignal ic
uc1606 65x132 matrix lcd controller-drivers version 1.32 1 t able of c ontent introduction .........................................................................................................1 ordering information ..........................................................................................2 block diagram.....................................................................................................3 pin description....................................................................................................4 control registers................................................................................................7 command table ..................................................................................................9 command description ......................................................................................10 lcd voltage settings .......................................................................................15 lcd display controls .......................................................................................18 host interface ....................................................................................................20 display data ram .............................................................................................24 reset & power management ............................................................................27 absolute maximum ratings .............................................................................31 specifications....................................................................................................32 ac characteristics............................................................................................33 physical dimensions ........................................................................................37 alignment mark information ............................................................................38 pad coordinates ...............................................................................................39 tray information................................................................................................42 revision history................................................................................................43
uc1606 65x132 matrix lcd controller-drivers version 1.32 1 uc1606 single-chip, ultra-low power passive matrix lcd controller-driver i ntroduction uc1606 is an advanced high-voltage mixed- signal cmos ic, especially designed for the display needs of ultra-low power hand-held devices. this chip employs ultrachip?s unique dcc (direct capacitor coupling) driver architecture to achieve near crosstalk free images. in addition to low power com and seg drivers, uc1606 contain all necessary circuits for high-v lcd power supply, bias voltage generation, timing generation and graphics data memory. advanced circuit design techniques are employed to minimize ex ternal component counts and reduce connector size while achieving extremely low power consumption. m ain a pplications ? cellular phones, smart phones, and other battery operated devices and/or portable instruments f eature h ighlights ? single chip controller-driver supports 65 com x 132 seg lcd. ? support industry standard 8-bit parallel interface (8080 or 6800), 4-wire spi (s8), and 3-wire spi (s9) serial interface. ? support four multiplexing rates (25, 33, 49, 65). ? self-configuring 6x charge pump with on- chip pumping capacitor requires only 3 external capacitors to operate. ? flexible data addressing/mapping schemes to support wide ranges of software models and lcd layout placements. ? software programmable 4 temperature compensation coefficients. ? on-chip bypass capacitor for v lcd makes v lcd bypass capacitor optional for small lcd panels. ? on-chip power-on reset and software reset commands, make rst pin optional. ? v dd (digital) range: 2.4v ~ 5v v dd (analog) range: 2.4v ~ 5v lcd v op range: 6.5v ~ 12.5v ? available in gold bump dies bump pitch: 70um min. bump gap: 24um min.
u ltra c hip high-voltage mixed-signal ic ?1999-2003 2 product specifications o rdering i nformation product id description UC1606XGAF 65 com x 132 seg lcd driver general notes a pplication i nformation for improved readability, the specification contains many appl ication data points. when application information is given, it is advisory and does not form part of the specification for the device. b are d ie d isclaimer all die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of ninety (90) days from the date of ultrachip?s delivery. there is no post waffle saw/pack testing performed on individual die. although the latest modern processes are utilized for wafer sawing and die pick-&-place into waffle pack carriers, ultrachip has no control of third party procedures in the handling, packing or assembly of the die. accordingly, it is the responsibility of the customer to test and quality their application in which the die is to be used. ultrachip assumes no liability for device functionality or performance of the die or systems after handling, packing or assembly of the die. l ife s upport a pplications these devices are not designed for use in life support appli ances, or systems where malfunction of these products can reasonably be expected to result in personal injuries. custom er using or selling these products for use in such applications do so at their own risk.
uc1606 65x132 matrix lcd controller-drivers version 1.32 3 b lock d iagram com drivers seg drivers power-on & reset control row address generator clock & timing gen. host interface control & status register command column address generator display data ram display data latches level shifters level shifter v lcd & bias generator page address generator data ram i/o buffer c b0 c l c b1
u ltra c hip high-voltage mixed-signal ic ?1999-2003 4 product specifications p in d escription name type pins description m ain p ower s upply v dd v dd2 v dd3 pwr v dd2 /v dd3 is the analog power supply and it should be connected to the same power source. v dd is the digital power supply and it should be connected to a voltage source that is no higher than v dd2 /v dd3 . minimize the trace resistance for v dd and v dd2 /v dd3 . v ss v ss2 gnd ground. connect v ss and v ss2 to the shared gnd pin. minimize the trace resistance for v ss and v ss2 . lcd p ower s upply v b1+ v b1? v b0+ v b0? pwr lcd bias voltages. these are the voltage sources to provide seg driving currents. these voltages are generated internally. connect capacitors of c bx value between v bx+ and v bx? . the resistance of these four traces directly affects the seg driving strength of the resulting lcd module. minimize the trace resistance is critical in achieving high quality image. v lcd-in v lcd-out pwr main lcd power supply. connect these pins together. a by-pass capacitor c l is optional. when c l is used, connect c l between v lcd and v ss , and keep the trace resistance under 300 ohm. n ote ? in cog applications, use one maximum width trace to connect v dd /v dd2 /v dd3 to the lcm pad to minimize trace resistance. however, to avoid nois e cross-coupling, insert a slit, 0.2~0.3mm long, between v dd /v dd2 /v dd3 . same treatment for v ss /v ss2 . ? recommended capacitor values: c b : 150 ~ 250x lcd load capacitance or 1.0uf (2v), whichever is higher. c l : 5nf ~ 20nf (16v) is appropr iate for most applications.
uc1606 65x132 matrix lcd controller-drivers version 1.32 5 name type pins description c onfiguration p in mr[1:0] i multiplex rate selection ?ll?: 25 ?lh?: 33 ?hl?: 49 ?hh?: 65 br[1:0] i lcd bias ratio. four bias ratios are supported for each mr setting. tc[1:0] i temperature compensation selection ?ll?: -0.0% ?lh?: -0.05% ?hl?: -0.1% ?hh?: -0.2% h ost i nterface ps[1:0] i parallel/serial. serial modes: ?ll?: serial (s8) ?lh?: serial (s9) parallel modes: ?hl?: 8080 ?hh?: 6800 cs0 cs1 i chip select. in parallel mode and s8 mode, chip is selected when cs0=?l? and cs1=?h?. when the chip is not selected, d[7:0] may be high impedance. *1 rst i when rst=?l?, all control registers are re -initialized by their default states. when rst is not used, connect the pin to v dd . cd i select command or display data for read/write operation. cd pin is not used in s9 modes, connect it to v dd or v ss. ?l?: command ?h?: display data wr0 wr1 i wr[1:0] controls the read/write operation of the host interface. in parallel mode, wr[1:0] meaning depends on whether the interface is in the 6800 mode or the 8080 mode. in serial interface modes, these two pins are not used. connect to v ss . d0~d7 i/o bi-directional bus for both seri al and parallel host interfaces. in s8 and s9 mode, leave unu sed pins open-circuit. ps=1x ps=0x d0 d0 sck d1 d1 d2 d2 sda d3 d3 d4 d4 d5 d5 d6 d6 d7 d7
u ltra c hip high-voltage mixed-signal ic ?1999-2003 6 product specifications name type pins description lcd d river o utput seg1 ~ seg132 hv seg (column) driver outputs. support up to 132 columns. leave unused drivers open-circuit. cic hv icon driver output. com1 ~ com64 hv com (row) driver outputs. support up to 64 rows. when mux rate is not 65, please use only com1~com(x-1), x=65, 49, 33, or 25, and leave com (x) ~ com64 open-circuit. m isc . p ins v ddx o auxiliary v dd . these pins are connected to the main v dd bus on chip, and they are provided to facilitate chip configurations in cog and cof applications. there is no need to connect v ddx to v dd externally. these pins should not be used to provide v dd power to the chip. eo o reserved. leave this pin open circuit. tst4 i test control. connect to v ss . tst[3:1] i/o test i/o pins. leave these pins open circuit during normal use. tp[3:1] i test control. leave these pins open circuit during normal use. *1 when read data is needed under joint bus (using mo re than one uc1606), following application circuits are recommended. each r/w (rd) pin should be separated from others. rd2 (r/w)1 cs1 cs wr e cs1 e vdd (uc1606)u1 r/w cs0 r/w (uc1606)u1 cs cs1 (uc1606)u1 cs0 cs1 (uc1606)u1 wr cs0 (r/w)2 rd1 cs0 rd wr e rd vdd for 6800 mode for 8080 mode
uc1606 65x132 matrix lcd controller-drivers version 1.32 7 c ontrol r egisters uc1606 contains registers which control the chip operat ion. these registers can be modified by commands. the following table is a summary of the control regi sters, their meaning and their default value. the commands supported by uc1606 are described in the next two sections, first a summary table, followed by a detailed description. name: the symbolic reference of the register byte. note that, some symbol names refer to collection of bits (flags) within one register byte. default: numbers shown in bold fonts are values after power-up-reset and system-reset . name bits default description sl 6 0h start line. mapping from com1 to display data ram. cr 8 0h return column address. us eful for cursor implementation. ca 8 0h display data ram column address (used in host to display data ram access) pa 4 0h display data ram page address (used in host to display data ram access) br 2 pin bias ratio. the ratio between v lcd and v bias . default value depends on br[1:0] pin configuration, and can be re-defined by set lcd bias ratio command. bias ratio (br[1:0]) mux rate 00 01 10 11 65 7.33 8.0 8.66 9.33 49 6.0 6.67 7.33 8.0 33/25 4.67 5.33 6.0 6.66 tc 2 pin temperature compensation (per o c). 00b: 0.0% 01b: -0.05% 10b: -0.1% 11b: -0.2% default value depends on tc[1:0] pin configuration. gn 3 3h gain, coarse setting of v bias and v lcd gn[2:0] 000 001 010 011 100 101 110 111 gain 1.43 1.58 1.72 1.89 2.08 2.28 2.49 2.72 pm 6 10h electronic potentiometer to fine tune v bias and v lcd mr 2 pin multiplexing rate: number of pixel rows: 00b: 25 01b: 33 10b: 49 11b: 65 default value depends on mr[1:0] pin configuration.
u ltra c hip high-voltage mixed-signal ic ?1999-2003 8 product specifications name bits default description om 2 ? operating modes (read only) 10b: sleep 11b: normal 01b: (not used) 00b: reset bz 1 ? busy with internal processes (reset, changing mode, etc.) ok for display ram read/write access. rs 1 reset in progress, host interface not ready pc 3 7h vlcd pump control. pc[0]: 0b:low lcd loading 1b: regular lcd loading pc[2:1]: 00b: external vlcd 01b: 4x 10b: 5x 11b: 6x apc0 8 6ch advanced product configuration. for ultrachip only. please do not use. dc 3 0h display control: dc[0]: pxv: pixels inverse (default: off ) dc[1]: apo: all pixels on (default:: off ) dc[2]: display on/off (default:: off ). ac 4 0h address control: ac[0]: wa: automatic column/page wrap around (default 0:off ) ac[1]: reserved (always set to 0) ac[2]: pid: pa (page address) auto increment direction ( 0: +1 1: -1) ac[3]: cum: cursor update mode, (default 0:off ) when cum=1, ca increment on write only, wrap around suspended lc 4 0h lcd mapping control: lc[0]: msf: msb first mapping option lc[1]: reserved (always set to 0) lc[2]: mx, mirror x (column sequence inversion) lc[3]: my, mirror y (row sequence inversion)
uc1606 65x132 matrix lcd controller-drivers version 1.32 9 c ommand t able the following is a list of host commands supported by uc1606 c/d: 0: control, 1: data w/r: 0: write cycle, 1: read cycle # useful data bits ? don?t care command c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 action default value 1 write data byte 1 0 # # # # # # # # write 1 byte n/a 2 read data byte 1 1 # # # # # # # # read 1 byte n/a 3 get status 0 1 bz mx de rs 0 00 0 get status n/a set column address lsb 0 0 0 0 0 0 # # # # set ca[3:0] 0 4 set column address msb 0 0 0 0 0 1 # # # # set ca[7:4] 0 5 set gain 0 0 0 0 1 0 0 # # # set gn[2:0] 011b 6 set pump control 0 0 0 0 1 0 1 # # # set pc[2:0] 111b 0 0 0 0 1 1 0 0 0 r 7 set adv. product config. (double byte command) 0 0 # # # # # # # # for ultrachip only. do not use. n/a 8 set start line 0 0 0 1 # # # # # # set sl[5:0] 0 9 set page address 0 0 1 0 1 1 # # # # set pa[3:0] 0 10 set potentiometer (double-byte command) 0 0 0 0 1 - 0 - 0 # 0 # 0 # 0 # 0 # 1 # set pm[5:0] pm=16 11 set ram address control 0 0 1 0 0 0 1 # 0 # set ac[2:0] 000b 12 set column mirroring 0 0 1 0 1 0 0 0 0 # set lc[3] 0 13 set all-pixel-on 0 0 1 0 1 0 0 1 0 # set dc[1] 0=disable 14 set inverse display 0 0 1 0 1 0 0 1 1 # set dc[0] 0=disable 15 set display enable 0 0 1 0 1 0 1 1 1 # set dc[2] 0=disable 16 set lcd mapping control 0 0 1 1 0 0 # # 0 # set lc[3:0] 0 17 system reset 0 0 1 1 1 0 0 0 1 0 system reset n/a 18 nop 0 0 1 1 1 0 0 0 1 1 no operation n/a 19 set lcd bias ratio 0 0 1 1 1 0 1 0 # # set br[1:0] pin 20 reset cursor mode 0 0 1 1 1 0 1 1 1 0 ac[3]=0, ca=cr n/a 21 set cursor mode 0 0 1 1 1 0 1 1 1 1 ac[3]=1, cr=ca n/a 0 0 1 1 1 0 0 1 tt 22 set test control (double byte command) 0 0 # # # # # # # # for ultrachip only. do not use. n/a * other than commands listed above, all other bi t patterns may result in undefined behavior.
u ltra c hip high-voltage mixed-signal ic ?1999-2003 10 product specifications c ommand description (1) write data to display memory action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 write data 1 0 8bits dat a write to sram (2) read data to display memory action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 read data 1 1 8bits data from sram write/read data byte (command 1,2 ) operation a ccesses display buffer ram based on page address (pa) register and column address (ca) r egister. to minimize bus interface cycles, pa and ca will be increased or decreased automatically depending on the setting of access control (ac) registers. pa and ca can also be programmed directly by issuing set page address and set column address commands. if w rap-a round (wa) is off (ac[0] = 0), ca will stop increasing after reaching the end of page (mc), and system programmers need to set the values of pa and ca explicitly. if wa is on (ac[0]=1), when ca reaches end of page, ca will be reset to 0 and pa will be increased or decreased by 1, depending on the setting of p age i ncrement d irection (pid, ac[2]). when pa reaches the boundary of ram (i.e. pa = 0 or 31), pa will be wrapped around to the ot her end of ram and continue. (3) get status action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 get status 0 1 bz mx de rs 0 0 0 0 status flag definitions: bz : busy with internal process. when bz=1 host interface can access if rs=0. mx : status of register lc[2], mirror x. de : display enable flag. de=1 when display enabled rs : reset in progress. if rs=1, host interface will be inaccessible. (4) set column address action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 set column address lsb ca[3:0] 0 0 0000 ca3 ca2 ca1 ca0 set column address msb ca[7:4] 0 0 0001 ca7 ca6 ca5 ca4 set the sram column address before write/read memory from host interface. ca possible value= 0-131 (5) set gain action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 set gain gn[2:0] 0 0 00100 gn2 gn1 gn0 program gain (gn[2:0]) . see section lcd v oltage s etting for more detail. gn[2:0] 000 001 010 011 100 101 110 111 gain 1.43 1.58 1.72 1.89 2.08 2.28 2.49 2.72
uc1606 65x132 matrix lcd controller-drivers version 1.32 11 (6) set pump control action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 set pump control pc[2:0] 0 0 00101 pc2 pc1 pc0 set pc[2:0] to program to use internal charge pump of external vlcd source: pc[0]: 0b : low lcd loading 1b : regular lcd loading pc[2:1]: 00b : external v lcd 01b : 4x 10b : 5x 11b : 6x (7) set advance product configuration action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 00 0011000 r set apc[0] (double byte command) 0 0 apc register parameter for ultrachip only. please do not use. (8) set start line action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 set start line sl[5:0] 0 0 01 sl5 sl4 sl3 sl2 sl1 sl0 set the start line number start line setting will scroll the displayed image up by sl rows. the valid value is between 0 (no scrolling) and 63. one example of the visual effect on lcd is illustrated in the figure below. 0 0 n n sl=0 sl=n com icon (cic) is not affected by this command. (9) set page address action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 set page address lsb pa [3:0] 0 0 1011 pa3 pa2 pa1 pa0 set the sram page address before write/ read memory from host interface. effective range of value = 0 ~ 8 image row 0 ???. image row n ???. image row 63 image row n ???. image row 63 image row 0 ??? image row n-1
u ltra c hip high-voltage mixed-signal ic ?1999-2003 12 product specifications (10) set potentiometer action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 00 1000000 1 set potentiometer pm [5:0] (double byte command) 0 0 - - pm5 pm4 pm3 pm2 pm1 pm0 program potentiometer (pm[5:0]). see section lcd v oltage s etting for more detail. effective range of pm value = 0 ~ 63 (11) set ram address control action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 set ac [2:0] 0 0 10001 ac2 ac1 ac0 program registers ac[2:0] fo r ram address control. ac[0] -- automatic column/page wrap around (wa). ac[1] ? reserved. (always set to 0). ac[2] ? pid, page address (pa) auto increment direction ( 0/1 = +/- 1 ) the column address will be reset to 0 and page addre ss will increase/decrease (+/- 1 depend on pid = 0/1 ) after column address equal to maximum column value. (12) set column mirroring action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 set column mirroring lc [3] 0 0 1010000 my set lc[2] for com (row) mirror (my). my is implemented by reversing the mapping or der between ram and com (row) electrodes. the data stored in ram is not affected by my command. my will have immediate effect on the display image. (13) set all pixel on action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 set all pixel on dc [1] 0 0 1010010 dc1 set dc[1] to force all seg drivers to output on signals. this function has no effect on the existing data stored in display ram. (14) set inverse display(pxv) action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 set inverse display dc [0] 0 0 1010011 dc0 set dc[0] to force all seg drivers to output the inverse of the data which stored in display memory. this function has no effect on the existing data stored in display ram. (15) set display enable action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 set display enable dc[2] 0 0 1010111 dc2 this command is for programming registers dc[2]. when dc[2] is set to 1, uc1606 will turn on com drivers and seg drivers.
uc1606 65x132 matrix lcd controller-drivers version 1.32 13 (16) set lcd mapping control action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 set lcd mapping control lc[3:0] 0 0 1100 my mx lc1 msf set lc[3:0] for com (row) mirror (my), seg (column) mirror (mx) and msb first or lsb first options (msf). my is implemented by reversing the mapping or der between ram and com (row) electrodes. the data stored in ram is not affected by my command. my will have immediate effect on the display image. mx is implemented by selecting the ca or 131- ca as write/read(from host interface) display ram column address so this function will only take effect after rewriting the ram data lc1 ? reserved. (always set to 0). msf is implemented by msb-lsb swapping. when msb first (lc[0] ) bit is set, data d[7:0] will be re- aligned then stored to ram. (17) system reset action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 system reset 0 0 1110001 0 this command will activate the system reset. the system will take about 5ms to reset (18) nop action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 no operation 0 0 1110001 1 this command is used for ?no operation?. (19) set lcd bias ratio action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 set bias ratio br [1:0] 0 0 111010 br1 br0 bias ratio definition: (20) reset cursor mode action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 return to cursor. ac[3]=0, ca=cr 0 0 1110111 0 this command is used to reset cursor up date mode function. see description below. bias ratio (br[1:0]) mux rate 00 01 10 11 65 7.33 8.0 8.66 9.33 49 6.0 6.67 7.33 8.0 33/25 4.67 5.33 6.0 6.66
u ltra c hip high-voltage mixed-signal ic ?1999-2003 14 product specifications (21) set cursor mode action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 set ac[3]=1 cr=ca 0 0 1110111 1 set cursor mode command is used to turn on cursor update mode function. ac[3] will be set to 1, register cr will be set to the value of register ca when ac[3]=1, column address (ca) will only incr ement with write ram operation but not on read ram operation. the address ca wraps around will also be suspended no matter what wa setting is. the purpose of this combination of features is to su pport ?read-modify-write? fo r cursor implementation. reset cursor mode command will clear cursor update mode flag (ac[3]=0), ca will be restored to previous ca value which is stored in cr, and ca, pa in crement will return to its normal condition. (22) set test control action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 00 111001 tt set tt (double byte command) 0 0 testing parameter this command is used for ultrachip production test ing. for ultrachip only. please do not use.
uc1606 65x132 matrix lcd controller-drivers version 1.32 15 lcd v oltage s ettings m ultiplex r ates four multiplex rates are supported in uc1606 (65, 49, 33, 25). mr is not software programmable. it is determined by pin programming. b ias s election bias ratio ( br ) is defined as the ratio between v lcd and v b , i.e. br = v lcd /v b , where v b = v b1+ ? v b1? = v b0+ ? v b0? . the reference bias ratio can be estimated by: 1 + mux uc1606 supports four bias ratios for each mr (mux rate) setting as illustrated below. bias ratio (br[1:0]) mux rate 00 01 10 11 65 7.33 8.0 8.66 9.33 49 6.0 6.67 7.33 8.0 33/25 4.67 5.33 6.0 6.66 table 1: br vs. mux rates br can be selected either by software program or by hardware pin wiring. v b g eneration v b is generated internally by uc1606. the value of v b is determined by three control registers: gn (gain), pm (potential meter), tc (temperature compensation) with the following relationship: pm b v gain v = where v pm is the output of an internal electronic potential meter. the value of v pm is given by: ref pm v pm v + = 1200 600 the value of gain is controlled by gn[2:0]. their relationship is shown below: gn[2:0] 000 001 010 011 100 101 110 111 gain 1.43 1.58 1.72 1.89 2.08 2.28 2.49 2.72 table 2: gain vs. gn value v ref temperature compensation v ref is a temperature compensated reference voltage. v ref increases automatically as ambient temperature cools down. four (4) different tem peratures compensated v ref can be selected via pin wiring. the compensation coefficient is given by the following table: tc[1:0] 00 01 10 11 % per o c 0.0 ?0.05 ?0.10 ?0.20 table 3: temperature compensation for all tc values, v ref are normalized to 1.25v at 25 o c. when selecting tc, make sure v b+ and v lcd stays within specified uc1606 ratings across entire operating temperature range. v lcd s election v lcd may be supplied either by internal charge pump or by external power supply. the source of v lcd is controlled by pc[2:1]. when v lcd is generated intern ally its value has the following relationship with v b : b lcd v biasratio v = given v ref = 1.25v at 25 o c, v lcd becomes: 25 . 1 1200 600 + ? pm gain biasratio v lcd (1) when pm=0, then equation (1) becomes: 6 . 1 gain biasratio v lcd ? (1b) l oad d riving s trength uc1606?s drivers and power supply circuits are designed to handle capacitance load of >2.5pf per pixel at v lcd =10.5v when v dd2 > 2.4v. uc1606 load driving strength is sensitive to ito impedance of power supply circuits (v dd , v ss , v b0/b1 , v lcd .) be sure to minimize these ito trace resistance for cog applications. p ower s upply c onfiguration uc1606 has built-in charge pump with on-chip pumping capacitors. the number of pump stages can be programmed by setting pc[2:1] register. make sure the chip is in reset mode before changing the value of pc[2:0]. given the same display quality, the lower pc[2:1] setting the more efficient is uc1606, but the weaker is the driving st rength. in application,
u ltra c hip high-voltage mixed-signal ic ?1999-2003 16 product specifications designers are recommended to verify the design with the highest setting first before trying lower settings to achieve better efficiency. due to the use of fully embedded power supply, built-in power ready detector, and drain circuit, there is no rigid power up or power down sequences for uc1606 controllers when using internal v lcd generator. on the other hand, caution must be exercised when external v lcd source is used. the general rule of thumb is to make sure display enable is off before connecting or disconnecting external v lcd sources.
uc1606 65x132 matrix lcd controller-drivers version 1.32 17 h i - v g enerator and bias reference circuit vlcdout vdd vdd3 cl vdd2 cb1 vdd uc1606 cb0 rl vss vlcdin vb1- vss2 (optional) vb0- vb1+ vb0+ f igure 1: reference circuit using inte rnal hi-v generator circuit vb1+ vdd vb1- cl vdd vdd3 (optional) rl vdd2 vlcdin vss2 external vlcd source vss vb0- cb0 cb1 vb0+ vlcdout uc1606 f igure 2: reference circuit using external hi-v source note ? recommended component values: c b : ~100x lcd load capacitance or 1.0uf (2v), whichever is higher. c l : 5nf ~ 20nf (16v) is appropr iate for most applications. r l : 10m . acts as a draining circuit when the power is abnormally shut down . ? the illustrated resistor values are for reference only. please optimize for specific requirements of each application.
u ltra c hip high-voltage mixed-signal ic ?1999-2003 18 product specifications lcd d isplay c ontrols c lock & t iming g enerator uc1606 contains a built-in system clock. all required components for the clock oscillator are built-in. no external parts are required. d river m odes com and seg drivers can be in either idle mode or active mode, controlled by display enable flag (dc[2]). when com drivers are in idle mode, their outputs are high-impedance (open circuit). when seg drivers are in idle mode, their outputs are connected to v ss . d river a rrangements the naming conventions are: com(x), where x=1~65, refers to the com driver for the x-th row of pixels on the lcd panel. the mapping of com(x) to lcd pixel rows is the same for all mr, mx and my settings. when mr is not 65, then com(x) ~ com65 (x = mr+1) should be left open circuit. display controls there are three groups of display control flags in the control register dc: driver enable (de), all- pixel-on (apo) and inverse (pxv). de has the overriding effect over pxv and apo. d river e nable (de) driver enable is controlled by the value of dc[2] via set display on command. when dc[2] is set to off (logic ?0?), both seg and com drivers will become idle and uc1606 will put itself into sleep mode to conserve power. when dc[2] is set to on, the de flag will become ?1?,and uc1606 will first exit from sleep mode, restore the power (v lcd , v bias etc.) and then turn on com drivers and proper seg drivers. a ll p ixels o n (apo) when set, this flag will force all active seg drivers to output on signals, disr egarding the data stored in the display buffer. this flag has no effect when display enable is off and it has no effect on data stored in ram. i nverse (pxv) when this flag is set to on, active seg drivers will output the inverse of the value it received from the display buffer ram (bit-wis e inversion). this flag has no impact on data stored in ram.
uc1606 65x132 matrix lcd controller-drivers version 1.32 19 ram w/r eo com1 com2 com3 seg1 seg2 figure 3: com and seg driving waveform
u ltra c hip high-voltage mixed-signal ic ?1999-2003 20 product specifications h ost i nterface as summarized in the table below, uc1606 supports two 8-bit parallel bus protocols and two serial bus protocols. designers can choose either the 8-bit parallel bus to achieve high data transfer rate, or use serial bus to create compact lcd modules and minimize connector pins. bus type 8080 6800 spi (s8) spi(s9) ps[1:0] 10b 11b 00b 01b cs[1:0] chip select cd control/data ? wr0 ___ __ wr _ _ r/w 0 0 wr1 ___ __ rd en 0 0 access read/write write only control & data pins d[7:0] 8-bit bus (tri-state) d0=sck, d2=sda * connect unused control pins to v dd or v ss. table 4: host interfaces choices p arallel i nterface the timing relationship between uc1606 internal control signal rd, wr and their associated bus actions are shown in the figure below. the display ram read interface is implemented as a two-stage pipeline. this ar chitecture requires that, every time memory address is modified, either in parallel mode or serial mode, by either set ca or set pa command, a dummy read cycle need to be performed before the actual data can propagate through the pipeline and be read from data port d[7:0]. there is no pipeline in write interface of display ram. data is transferred directly from bus buffer to internal ram on the rising edges of write pulses. l lsb d l d l+k c msb c lsb dummy d c d c+1 m msb m lsb l l+k l+k+1 c c+1 c+2 c+3 m d l d l+k dummy d c d c+1 d c+2 external cd ___ wr __ rd d[7:0] internal write read data latch column address figure 4: parallel interface & related internal signals
uc1606 65x132 matrix lcd controller-drivers version 1.32 21 s erial i nterface uc1606 supports two serial modes, 4-wire mode (ps=?ll?), and 3-wire mode (ps=?lh?). the mode of interface is determined during power-up process by the value of ps[1:0]. 4- wire s erial i nterface (s8) only write operations are su pported in 4-wire serial mode. pin cs[1:0] are used for chip select and bus cycle reset. pin cd is used to determine the content of the data been transferred. during each write cycle, 8 bits of data, msb first, are latched on eight rising sck edges into an 8-bit data holder. if cd=0, the data byte will be decoded as command. if cd=1, this 8-bit will be treated as data and transferred to proper address in the display data ram on the rising edge of the last sck pulse. pin cd is examined when sck is pulled low for the lsb (d0) of each token. cs1/0 sda sck cd d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 figure 5.a: 4-wire serial interface (s8) 3- wier s erial i nterface (s9) only write operations are su pported in 3-wire serial mode. pin cs[1:0] are used for chip select and bus cycle reset. on each write cycle, the first bit is cd, which determines the content of the following 8 bits of data, msb first. these 8 command or data bits are latched on rising sck edges into an 8-bit data holder. if cd=0, the data byte will be decoded as command. if cd=1, this 8-bit will be treated as data and transferred to proper address in the display data ram at the rising edge of the last sck pulse. by sending cd information explicitly in the bit stream, control pin cd is not used, and should be connected to either v dd or v ss . the toggle of cs0 (or cs1) for each byte of data/command is recommended but optional. cs0 sda sck cd d7 d6 d5 d4 d3 d2 d1 d0 cd d7 d6 figure 5.b: 3-wire serial interface (s9)
u ltra c hip high-voltage mixed-signal ic ?1999-2003 22 product specifications h ost interface reference circuit wr0(wr) gnd rd vss rst vdd cd vdd wr vcc cd cs1 vdd d7-d0 d7-d0 cs0 uc1606 decoder vdd iorq address mpu ps0 ps1 wr1(rd) f igure 6: 8080/8bit parallel mode reference circuit cs0 rst address wr1(e) ps1 gnd e uc1606 vcc mpu vdd d7-d0 wr0(r/w) vdd r/w vdd decoder cd iorq vss vdd cd cs1 ps0 d7-d0 f igure 7: 6800/8bit parallel mode reference circuit
uc1606 65x132 matrix lcd controller-drivers version 1.32 23 mpu gnd rst vdd decoder vdd cs0 vdd uc1606 cd ps1 iorq ps0 sck cs1 wr0 vcc wr1 sda address sck(d0) cd sda(d2) vss f igure 8: serial-8 serial m ode reference circuit ps1 iorq cs0 uc1606 vdd decoder mpu sck(d0) address rst vdd sck gnd cs1 wr0 vcc ps0 sda(d2) vdd sda wr1 vdd vss f igure 9: serial-9 serial m ode reference circuit note: rst pin is optional. when rst pin is not used, connect the pin to vdd.
u ltra c hip high-voltage mixed-signal ic ?1999-2003 24 product specifications d isplay d ata ram d ata o rganization the display data is 1-bit per pixel and stored in a dual port static ram (ram, for display data ram). the ram size is 65 x 132 for uc1606. this array of data bits is further org anized into pages of 8 bit slices to facilitate parallel bus interface. when mirror x (mx, lc[2]) is off, the 1 st column of lcd pixels will correspond to the bits of the first byte of each page, the 2 nd column of lcd pixels correspond to the bits of the second byte of each page, etc. msb f irst or lsb f irst there are two options to map d[7:0] to ram, msb first (msf=1), or lsb first (msf=0), as illustrated in next page. d isplay d ata ram a ccess the memory used in uc1606 display data ram (ram) is a special purpose dual port ram which allows asynchronous access to both its column and row data. thus, ram can be independently accessed both for host interface and for display operations. d isplay d ata ram a ddressing a host interface (hi) memory access operation starts with specifying page address (pa) and column address (ca) by issuing set page address and set column address commands. if wrap-around (wa, ac[0]) is off (0), ca will stop increasing after reaching the end of page , and system programmers need to set the values of pa and ca explicitly.
uc1606 65x132 matrix lcd controller-drivers version 1.32 25 line pa[3:0] 0 1 addecss sl=0 sl=16 sl=0 sl=0 sl=25 sl=25 d0 d7 00h c1 c49 c64 c48 c25 c9 d1 d6 01h c2 c50 c63 c47 c24 c8 d2 d5 02h c3 c51 c62 c46 c23 c7 d3 d4 03h c4 c52 c61 c45 c22 c6 d4 d3 04h c5 c53 c60 c44 c21 c5 d5 d2 05h c6 c54 c59 c43 c20 c4 d6 d1 06h c7 c55 c58 c42 c19 c3 d7 d0 07h c8 c56 c57 c41 c18 c2 d0 d7 08h c9 c57 c56 c40 c17 c1 d1 d6 09h c10 c58 c55 c39 c16 --- d2 d5 0ah c11 c59 c54 c38 c15 --- d3 d4 0bh c12 c60 c53 c37 c14 --- d4 d3 0ch c13 c61 c52 c36 c13 --- d5 d2 0dh c14 c62 c51 c35 c12 --- d6 d1 0eh c15 c63 c50 c34 c11 --- d7 d0 0fh c16 c64 c49 c33 c10 --- d0 d7 10h c17c1c48c32c9 --- d1 d6 11h c18c2c47c31c8 --- d2 d5 12h c19c3c46c30c7 --- d3 d4 13h c20c4c45c29c6 --- d4 d3 14h c21c5c44c28c5 --- d5 d2 15h c22c6c43c27c4 --- d6 d1 16h c23c7c42c26c3 --- d7 d0 17h c24c8c41c25c2 --- d0 d7 18h c25c9c40c24c1 --- d1 d6 19h c26 c10 c39 c23 c64 c48* d2 d5 1ah c27c11c38c22c63c47 d3 d4 1bh c28c12c37c21c62c46 d4 d3 1ch c29c13c36c20c61c45 d5 d2 1dh c30c14c35c19c60c44 d6 d1 1eh c31c15c34c18c59c43 d7 d0 1fh c32c16c33c17c58c42 d0 d7 20h c33c17c32c16c57c41 d1 d6 21h c34c18c31c15c56c40 d2 d5 22h c35c19c30c14c55c39 d3 d4 23h c36c20c29c13c54c38 d4 d3 24h c37c21c28c12c53c37 d5 d2 25h c38c22c27c11c52c36 d6 d1 26h c39c23c26c10c51c35 d7 d0 27h c40 c24 c25 c9 c50 c34 d0 d7 28h c41 c25 c24 c8 c49 c33 d1 d6 29h c42 c26 c23 c7 c48 c32 d2 d5 2ah c43 c27 c22 c6 c47 c31 d3 d4 2bh c44 c28 c21 c5 c46 c30 d4 d3 2ch c45 c29 c20 c4 c45 c29 d5 d2 2dh c46 c30 c19 c3 c44 c28 d6 d1 2eh c47 c31 c18 c2 c43 c27 d7 d0 2fh c48 c32 c17 c1 c42 c26 d0 d7 30h c49 c33 c16 --- c41 c25 d1 d6 31h c50 c34 c15 --- c40 c24 d2 d5 32h c51 c35 c14 --- c39 c23 d3 d4 33h c52 c36 c13 --- c38 c22 d4 d3 34h c53 c37 c12 --- c37 c21 d5 d2 35h c54 c38 c11 --- c36 c20 d6 d1 36h c55 c39 c10 --- c35 c19 d7 d0 37h c56 c40 c9 --- c34 c18 d0 d7 38h c57 c41 c8 --- c33 c17 d1 d6 39h c58 c42 c7 --- c32 c16 d2 d5 3ah c59 c43 c6 --- c31 c15 d3 d4 3bh c60 c44 c5 --- c30 c14 d4 d3 3ch c61 c45 c4 --- c29 c13 d5 d2 3dh c62 c46 c3 --- c28 c12 d6 d1 3eh c63 c47 c2 --- c27 c11 d7 d0 3fh c64 c48 c1 --- c26 c10 1000 d0 d7 40h page 8 cic cic cic cic cic cic 65 49 65 49 0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg128 seg129 seg130 seg131 seg132 1 seg132 seg131 seg130 seg129 seg128 seg127 seg126 seg125 seg5 seg4 seg3 seg2 seg1 mux my=1 page 7 page 6 my=0 0111 page 0 page 1 page 2 page 3 page 4 0101 page 5 mx 0110 msf 0000 0001 0010 0011 0100 example for memory mapping: let mx = 0, my = 0, sl = 0, msf = 0, according to the data shown in the above table: ? page 0 seg 1: 00011111b ? page 0 seg 2: 11001100b
u ltra c hip high-voltage mixed-signal ic ?1999-2003 26 product specifications mx i mplementation column mirroring (mx) is implemented by selecting either (ca) or (64?ca) as the ram column address. changing mx affects the data written to the ram. since mx has no effect on data already stored in ram, changing mx does not have immediate effect on the displayed pattern. to refresh the display, refresh the data stored in ram after setting mx. r ow s canning for each field, the scanni ng starts at com1 through comx, where x depends on the setting of mr. com electrode scanning (row scanning) orders are not affected by start line (sl) or mirror y (my, lc[3]). when my is 0, the effect of sl having a value k is to change the mapping of com1 to the k -th bit slice of data stored in display ram. visually, sl having a non-zero value is equivalent to scrolling lcd display up by sl rows. ram a ddress g eneration the mapping of the data stored in the display sram and the scanning electrodes can be obtained by combining the fixed row scanning sequence and the following ram address generation formula. during the display operation, the ram line address generation can be mathematically represented as following: for the 1 st line period of each field line = sl otherwise line = mod( line +1, 64 ) where mod is the modular operator, and line is the bit slice line address of ram to be outputted to seg drivers. line 0 corresponds to the first bit-slice of data in ram. the above line generation formula produces the ?loop around? effect as it effectively resets line to 0 when line+1 reaches 64 . effects such as page scro lling, page swapping can be emulated by changing sl dynamically. my i mplementation row mirroring (my) is implemented by reversing the mapping order between com electrodes and ram, i.e. the mathematical address generation formula becomes: for the 1 st line period of each field line = mod( sl + mux-1 , 64 ) where mux = 25, 33, 49, or 65. otherwise line = mod( line-1 , 64 ) visually, the effect of my is equivalent to flipping the display upside down. the data stored in display ram is not affected by my.
uc1606 65x132 matrix lcd controller-drivers version 1.32 27 r eset & p ower m anagement t ypes of r eset uc1606 has two different types of reset: power-on-reset and system-reset . power-on-reset is performed right after v dd is connected to power. power-on-reset will first wait for about ~20ms, depending on the time required for v dd to stabilize, and then trigger the system reset . system reset can also be activated by software command or by connecting rst pin to ground. in the following discussions, reset means system reset . r eset s tatus when uc1606 enters reset sequence: ? operation mode will be ?reset? ? system status bits rs and bz will stay as ?1? until the reset process is completed. when rs=1, the ic will only respond to read status command. all other commands are ignored. ? all control registers are reset to default values. refer to control registers for details of their default values. o peration m odes uc1606 has three operating modes (om): reset, normal, sleep. mode reset sleep normal om 00 10 11 host interface active active active clock off off on lcd drivers off off on charge pump off off on draining circuit on off off table 5: operating modes c hanging o peration m ode in addition to power-on reset, two commands will initiate om transitions: set display enable , and system reset . when dc[2] is modified by set display enable , om will be updated automatically. there is no other action required to enter sleep mode. for maximum energy utilization, sleep mode is designed to retain charges stored in external capacitors c b0 , c b1 , and c l . to drain these capacitors, use reset command to activate the on- chip draining circuit. action mode om set driver enable to ?0? sleep 10 set driver enable to ?1? normal 11 reset command or rst_ pin pulled ?l? power on reset reset 00 table 6: om changes even though uc1606 consumes very little energy in sleep mode (typically 5ua or less), since all capacitors are still charged, the leakage through com drivers may damage the lcd over the long term. it is therefore recommended to use sleep mode only for brief displa y off operations, such as full-frame screen updates, and to use reset for extended screen off operations. e xiting s leep m ode uc1606 contains internal logic to check whether v lcd and v bias are ready before releasing com and seg drivers from their idle states. when exiting sleep or reset mode, com and seg drivers will not be activated until uc1606 internal voltage sources are restored to their proper values.
u ltra c hip high-voltage mixed-signal ic ?1999-2003 28 product specifications p ower -u p s equence uc1606 power-up sequence is simplified by built-in ?power ready? flags and the automatic invocation of system-reset command after power-on-reset . system programmers are onl y required to wait 20~ 30 ms before the cpu starting to issue commands to uc1606. no additional time sequences are required between enabling the charge pump, turning on the display drivers, writing to ram or any other commands. p ower -d own s equence to prevent the charge stored in capacitors c bx+ , c bx? , and c l from damaging the lcd when v dd is switched off, use reset mode to enable the built-in draining circuit and discharge these capacitors. the draining resistor is 1k ohm for both v lcd and v b+ . it is recommended to wait 3 x rc for v lcd and 1.5 x rc for v b+ . for example, if c l is 10nf, then the draining time required for v lcd is 3~5ms. when internal v lcd is not used, uc1606 will not drain v lcd during reset. system designers need to make sure external v lcd source is properly drained off before turning off v dd . turn on vdd set lcd bias ratio (br) set gain (gn) set potential meter (pm) set display enable wait 20~30 ms figure 10: reference power-up sequence turn off vdd reset command wait 3~5 ms figure 11: reference power-down sequence
uc1606 65x132 matrix lcd controller-drivers version 1.32 29 s ample p ower c ommand s equences the following tables are examples of command seque nce for power-up, power-down and display on/off operations. these are only to demonstrate some ? typical, generic ? scenarios. designers are encouraged to study related sections of the datasheet and find out what the best parameters and control sequences for their specific design needs. c/d the type of the interface cycle. it can be either command (0) or data (1) w/r the direction of data flow of the cycl e. it can be either write (0) or read (1). type r equired: these items are required c ustomer: these items are not necessary if cu stomer parameters are the same as default a dvanced: we recommend new users to skip these commands and use default values. o ptional: these commands depend on what users want to do. p ower -u p type c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 chip action comments r ? ? ? ? ? ? ? ? ? ? automatic power-on reset. wait ~30ms after v dd is on c 0 0 1 1 0 0 # # 0 # (16) set lcd mapping set up lcd specific parameters such as format, mx, my, msf, etc. c 0 0 1 1 1 0 1 0 # # (19) set bias ratio r 0 0 0 0 1 0 0 # # # (5) set gain r 0 0 0 0 1 # 0 # 0 # 0 # 0 # 0 # 0 # 1 # (10) set pm c 1 . . 1 0 . . 0 # . . # # . . # # . . # # . . # # . . # # . . # # . . # # . . # write display ram set up display image r 0 0 1 0 1 0 1 1 1 1 (15) set display enable p ower -d own type c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 chip action comments r 0 0 1 1 1 0 0 0 1 0 (17) system reset r ? ? ? ? ? ? ? ? ? ? draining capacitor wait 3~5ms before v dd off
u ltra c hip high-voltage mixed-signal ic ?1999~2003 30 product specifications b rief d isplay -off type c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 chip action comments r 0 0 1 0 1 0 1 1 1 0 (15) set display disable c 1 . . 1 0 . . 0 # . . # # . . # # . . # # . . # # . . # # . . # # . . # # . . # write display ram set up display image (image update is optional. data in the ram is retained through the sleep state.) r 0 0 1 0 1 0 1 1 1 1 (15) set display enable * this is only recommended for very brief display off (under 10ms). if image becomes unstable use the extended display off approach shown below. e xtended d isplay -off type c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 chip action comments r 0 0 1 1 1 0 0 0 1 0 (17) system reset. c b1 , c b1 , c lcd discharged. ? ? ? ? ? ? ? ? ? ? ? extended display off z z z z . . . ? ? ? ? ? ? ? ? ? ? ? system waking up c 0 0 1 1 0 0 # # 0 # (16) set lcd mapping set up lcd specific parameters such as format, mx, my, msf, etc. c 1 . . 1 0 . . 0 # . . # # . . # # . . # # . . # # . . # # . . # # . . # # . . # write display ram set up display image (image update is optional. data in the ram is retained through the reset state.) c 0 0 1 1 1 0 1 0 # # (19) set bias ratio r 0 0 0 0 1 0 0 # # # (5) set gain r 0 0 0 0 1 # 0 # 0 # 0 # 0 # 0 # 0 # 1 # (10) set pm r 0 0 1 0 1 0 1 1 1 1 (17) set display enable * the sequence is basically the same as the power up sequence, except power-on reset is replaced by system reset command, and an extended idle time in between.
uc1606 65x132 matrix lcd controller-drivers version 1.32 31 a bsolute m aximum r atings in accordance with iec134, note 1, 2 and 3. symbol parameter min. max. unit v dd logic supply voltage -0.3 +5.5 v v dd2 lcd generator supply voltage -0.3 +5.5 v v dd3 analog circuit supply voltage -0.3 +5.5 v v lcd lcd generated voltage -0.3 +15.5 v v in any input voltage -0.3 v dd + 0.3 v t opr operating temperature range -30 +85 o c t str storage temperature -55 +125 o c notes 1. v dd based on v ss = 0v 2. stress values listed above may cause permanent damages to the device.
u ltra c hip high-voltage mixed-signal ic ?1999~2003 32 product specifications s pecifications dc c haracteristics symbol parameter conditions min. typ. max. unit v dd supply for digital circuit 2.4 3.0 5.0 v v dd2/3 supply for bias & pump 2.4 3.0 5.0 v v lcd charge pump output v dd2/3 >= 2.4v, 25 o c 9.5 13.5 v v d lcd data voltage v dd2/3 >= 2.4v, 25 o c 1.2 v v il input logic low 0.2v dd v v ih input logic high 0.8v dd v v ol output logic low 0.2v dd v v oh output logic high 0.8v dd v i il input leakage current 1.5 a r 0(seg) seg output impedance v lcd = 9v 3 4 k ? r 0(com) com output impedance v lcd = 9v 3.5 4.5 k ? f clk internal clock frequency 183 190 196 khz p ower c onsumption vdd = 2.8, bias ratio = 9.33, gain = 1.43, pm = 32 , pl = regular lcd loading, mr = 65, bus mode = 6800, c l = 20nf, cb = 1uf. all outputs are open-circuit. display pattern conditions typ.( a) max.( a) all-off bus = idle 249 600 2-pixel checker bus = idle 451 600
uc1606 65x132 matrix lcd controller-drivers version 1.32 33 ac c haracteristics figure 12: parallel bus timing charac teristics (for 8080 mcu) (vdd=2.4v to 3.0v, ta= ?30 to +85 o c) symbol signal description condition min. max. units t as80 t ah80 cd address setup time address hold time 25 50 ? ns t cy80 system cycle time 300 ? ns t pwr80 wr1 pulse width (read) 85 ? ns t pww80 wr0 pulse width (write) 85 ? ns t hpw80 wr0, wr1 high pulse width 85 ? ns t ds80 t dh80 d0~d7 data setup time data hold time 40 15 ? ns t acc80 t od80 read access time output disable time c l = 100pf ? 10 140 100 ns t cssa80 t cssd80 t csh80 cs1/cs0 chip select setup time 15 15 30 ns (vdd=3.0v to 4.0v, ta= ?30 to +85 o c) symbol signal description condition min. max. units t as80 t ah80 cd address setup time address hold time 20 45 ? ns t cy80 system cycle time 166 ? ns t pwr80 wr1 pulse width (read) 65 ? ns t pww80 wr0 pulse width (write) 65 ? ns t hpw80 wr0, wr1 high pulse width 65 ? ns t ds80 t dh80 d0~d7 data setup time data hold time 30 10 ? ns t acc80 t od80 read access time output disable time c l = 100pf ? 10 65 45 ns t cssa80 t cssd80 t csh80 cs1/cs0 chip select setup time 10 10 20 ns cd t as80 t ah80 cs0 cs1 t cssa80 t cy80 t csh80 t cssd80 t pwr80 , t pww80 t hpw80 wr0, wr1 t ds80 t dh80 write d[7:0] t acc80 t od80 read d[7:0]
u ltra c hip high-voltage mixed-signal ic ?1999~2003 34 product specifications figure 13: parallel bus timing charac teristics (for 6800 mcu) (vdd=2.4v to 3.0v, ta= ?30 to +85 o c) symbol signal description condition min. max. units t as68 t ah68 cd address setup time address hold time 25 50 ? ns t cy68 system cycle time 300 ? ns t pwr68 wr1 pulse width (read) 85 ? ns t pww68 pulse width (write) 85 ? ns t lpw68 low pulse width 85 ? ns t ds68 t dh68 d0~d7 data setup time data hold time 40 15 ? ns t acc68 t od68 read access time output disable time c l = 100pf ? 10 140 100 ns t cssa68 t cssd68 t csh68 cs1/cs0 chip select setup time 15 15 30 ns (vdd=3.0v to 4.0v, ta= ?30 to +85 o c) symbol signal description condition min. max. units t as68 t ah68 cd address setup time address hold time 20 45 ? ns t cy68 system cycle time 166 ? ns t pwr68 wr1 pulse width (read) 65 ? ns t pww68 pulse width (write) 65 ? ns t lpw68 low pulse width 65 ? ns t ds68 t dh68 d0~d7 data setup time data hold time 30 10 ? ns t acc68 t od68 read access time output disable time c l = 100pf ? 10 70 50 ns t cssa68 t cssd68 t csh68 cs1/cs0 chip select setup time 10 10 20 ns cd t as68 t ah68 cs0 cs1 t cssa68 t cy68 t csh68 t cssd68 t pwr68 , t pww68 t lpw68 wr1 t ds68 t dh68 write d[7:0] t acc68 t od68 read d[7:0]
uc1606 65x132 matrix lcd controller-drivers version 1.32 35 figure 14: serial bus timing characteristics (vdd=2.4v to 3.0v, ta= ?30 to +85 o c) symbol signal description condition min. max. units t ass address setup time 15 ? ns t ahs cd address hold time 40 ? ns t cys system cycle time 250 ? ns t lpws low pulse width 100 ? ns t hpws sck high pulse width 100 ? ns t dss t dhs sda data setup time data hold time 90 90 ? ns t cssas t cssds t cshs cs1/cs0 chip select setup time 10 10 150 ns (vdd=3.0v to 4.0v, ta= ?30 to +85 o c) symbol signal description condition min. max. units t ass address setup time 10 ? ns t ahs cd address hold time 20 ? ns t cys system cycle time 200 ? ns t lpws low pulse width 75 ? ns t hpws sck high pulse width 75 ? ns t dss t dhs sda data setup time data hold time 50 50 ? ns t cssas t cssds t cshs cs1/cs0 chip select setup time 10 10 100 ns cd t ass t ahs cs0 cs1 t cssas t cys t cshs t cssds t lpws t hpws sck t dss t dhs sda
u ltra c hip high-voltage mixed-signal ic ?1999~2003 36 product specifications rst t rw figure 15: reset characteristics (vdd=2.4v to 3.0v, ta= ?30 to +85 o c) symbol signal description condition min. max. units t rw rst reset low pulse width 240 ? ns (vdd=3.0v to 4.0v, ta= ?30 to +85 o c) symbol signal description condition min. max. units t rw rst reset low pulse width 200 ? ns
uc1606 65x132 matrix lcd controller-drivers version 1.32 37 p hysical d imensions d ie s ize : 9.862 mm x 1.647 mm d ie t hickness : 0.625mm b ump height : 17m 1m (within die) a u b ump size : 86 x 46m 2 (typ.) 66 x 49 m 2 (typ.) m inimum b ump pitch : 70m (typ.) m inimum b ump g ap : 24m (typ.) c oordinate origin : chip center p ad reference : pad center (drawings and coordinates are in the circuit/bump view)
u ltra c hip high-voltage mixed-signal ic ?1999~2003 38 product specifications a lignment m ark i nformation (0,0) d-left mark d-right mark c r r c oordinates : d-left mark center d-right mark center x y x y -4610.0 -430.7 4610.0 -430.7 s ize : r: 18.0 m; r: 9.0 m s hape of the alignment mark : n ote : a lignment mark is on metal3 under passivation. t op m etal and p assivation : f or n on -otp p rocess c ross -s ection
uc1606 65x132 matrix lcd controller-drivers version 1.32 39 p ad c oordinates # name x y w h 1 com1 -4813 698 86 46 2 com3 -4813 628 86 46 3 com5 -4813 558 86 46 4 com7 -4813 488 86 46 5 com9 -4813 418 86 46 6 com11 -4813 348 86 46 7 com13 -4813 278 86 46 8 com15 -4813 208 86 46 9 com17 -4813 138 86 46 10 com19 -4813 68 86 46 11 com21 -4813 -2 86 46 12 com23 -4813 -72 86 46 13 com25 -4813 -142 86 46 14 com27 -4813 -212 86 46 15 com29 -4813 -282 86 46 16 com31 -4813 -352 86 46 17 com33 -4813 -422 86 46 18 com35 -4813 -492 86 46 19 com37 -4813 -562 86 46 20 com39 -4813 -632 86 46 21 com41 -4813 -702 86 46 22 com43 -4612 -706 46 86 23 com45 -4542 -706 46 86 24 com47 -4472 -706 46 86 25 com49 -4402 -706 46 86 26 com51 -4332 -706 46 86 27 com53 -4262 -706 46 86 28 com55 -4192 -706 46 86 29 com57 -4122 -706 46 86 30 com59 -4052 -706 46 86 31 com61 -3982 -706 46 86 32 com63 -3912 -706 46 86 33 cic -3842 -706 46 86 34 nc -3764 -706 46 86 35 eo -3694 -706 46 86 36 vddx -3624 -706 46 86 37 cs0 -3554 -706 46 86 38 cs1 -3484 -706 46 86 39 tst4 -3414 -706 46 86 40 rst -3344 -706 46 86 41 cd -3274 -706 46 86 42 wr0 -3204 -706 46 86 43 wr1 -3134 -706 46 86 44 d0 -3064 -706 46 86 45 d1 -2994 -706 46 86 46 d2 -2924 -706 46 86 47 d3 -2854 -706 46 86 48 d4 -2784 -706 46 86 49 d5 -2714 -706 46 86 # name x y w h 50 d6 -2644 -706 46 86 51 d7 -2574 -706 46 86 52 vdd -2394 -723 86 46 53 vdd -2287 -723 86 46 54 vdd -2180 -723 86 46 55 vdd -2074 -723 86 46 56 vdd -1967 -723 86 46 57 vdd2 -1769 -723 86 46 58 vdd2 -1663 -723 86 46 59 vdd2 -1556 -723 86 46 60 vdd2 -1449 -723 86 46 61 vdd3 -1343 -723 86 46 62 vss -1054 -723 86 46 63 vss -947 -723 86 46 64 vss -841 -723 86 46 65 vss -734 -723 86 46 66 vss -627 -723 86 46 67 vss2 -430 -723 86 46 68 vss2 -323 -723 86 46 69 vss2 -216 -723 86 46 70 vss2 -110 -723 86 46 71 vb1+ 125 -723 86 46 72 vb1+ 231 -723 86 46 73 vb1+ 338 -723 86 46 74 tp3 436 -724 66 49 75 tp2 526 -724 66 49 76 tp1 616 -724 66 49 77 ps0 764 -706 46 86 78 ps1 904 -706 46 86 79 vddx 974 -706 46 86 80 mr0 1114 -706 46 86 81 mr1 1254 -706 46 86 82 vb1- 1394 -706 46 86 83 vb1- 1464 -706 46 86 84 vb1- 1534 -706 46 86 85 vb1- 1604 -706 46 86 86 vb0- 1744 -706 46 86 87 vb0- 1814 -706 46 86 88 vb0- 1884 -706 46 86 89 vb0- 1954 -706 46 86 90 br0 2094 -706 46 86 91 br1 2234 -706 46 86 92 vddx 2304 -706 46 86 93 tc0 2444 -706 46 86 94 tc1 2584 -706 46 86 95 vb0+ 2724 -706 46 86 96 vb0+ 2794 -706 46 86 97 vb0+ 2864 -706 46 86 98 vb0+ 2934 -706 46 86
u ltra c hip high-voltage mixed-signal ic ?1999~2003 40 product specifications # name x y w h 99 tst1 3074 -706 46 86 100 tst2 3144 -706 46 86 101 tst3 3214 -706 46 86 102 vlcdin 3354 -706 46 86 103 vlcdout 3424 -706 46 86 104 vlcdin 3494 -706 46 86 105 vlcdout 3634 -706 46 86 106 vdd2 3704 -706 46 86 107 vdd2 3774 -706 46 86 108 com64 3844 -706 46 86 109 com62 3914 -706 46 86 110 com60 3984 -706 46 86 111 com58 4054 -706 46 86 112 com56 4124 -706 46 86 113 com54 4194 -706 46 86 114 com52 4264 -706 46 86 115 com50 4334 -706 46 86 116 com48 4404 -706 46 86 117 com46 4474 -706 46 86 118 com44 4544 -706 46 86 119 com42 4614 -706 46 86 120 com40 4813 -702 86 46 121 com38 4813 -632 86 46 122 com36 4813 -562 86 46 123 com34 4813 -492 86 46 124 com46 4813 -422 86 46 125 com30 4813 -352 86 46 126 com28 4813 -282 86 46 127 com26 4813 -212 86 46 128 com24 4813 -142 86 46 129 com22 4813 -72 86 46 130 com20 4813 -2 86 46 131 com18 4813 68 86 46 132 com16 4813 138 86 46 133 com14 4813 208 86 46 134 com12 4813 278 86 46 135 com10 4813 348 86 46 136 com8 4813 418 86 46 137 com6 4813 488 86 46 138 com4 4813 558 86 46 139 com2 4813 628 86 46 140 cic 4813 698 86 46 141 seg1 4585 706 46 86 142 seg2 4515 706 46 86 143 seg3 4445 706 46 86 144 seg4 4375 706 46 86 145 seg5 4305 706 46 86 146 seg6 4235 706 46 86 147 seg7 4165 706 46 86 148 seg8 4095 706 46 86 149 seg9 4025 706 46 86 # name x y w h 150 seg10 3955 706 46 86 151 seg11 3885 706 46 86 152 seg12 3815 706 46 86 153 seg13 3745 706 46 86 154 seg14 3675 706 46 86 155 seg15 3605 706 46 86 156 seg16 3535 706 46 86 157 seg17 3465 706 46 86 158 seg18 3395 706 46 86 159 seg19 3325 706 46 86 160 seg20 3255 706 46 86 161 seg21 3185 706 46 86 162 seg22 3115 706 46 86 163 seg23 3045 706 46 86 164 seg24 2975 706 46 86 165 seg25 2905 706 46 86 166 seg26 2835 706 46 86 167 seg27 2765 706 46 86 168 seg28 2695 706 46 86 169 seg29 2625 706 46 86 170 seg30 2555 706 46 86 171 seg31 2485 706 46 86 172 seg32 2415 706 46 86 173 seg33 2345 706 46 86 174 seg34 2275 706 46 86 175 seg35 2205 706 46 86 176 seg36 2135 706 46 86 177 seg37 2065 706 46 86 178 seg38 1995 706 46 86 179 seg39 1925 706 46 86 180 seg40 1855 706 46 86 181 seg41 1785 706 46 86 182 seg42 1715 706 46 86 183 seg43 1645 706 46 86 184 seg44 1575 706 46 86 185 seg45 1505 706 46 86 186 seg46 1435 706 46 86 187 seg47 1365 706 46 86 188 seg48 1295 706 46 86 189 seg49 1225 706 46 86 190 seg50 1155 706 46 86 191 seg51 1085 706 46 86 192 seg52 1015 706 46 86 193 seg53 945 706 46 86 194 seg54 875 706 46 86 195 seg55 805 706 46 86 196 seg56 735 706 46 86 197 seg57 665 706 46 86 198 seg58 595 706 46 86 199 seg59 525 706 46 86 200 seg60 455 706 46 86
uc1606 65x132 matrix lcd controller-drivers version 1.32 41 # name x y w h 201 seg61 385 706 46 86 202 seg62 315 706 46 86 203 seg63 245 706 46 86 204 seg64 175 706 46 86 205 seg65 105 706 46 86 206 seg66 35 706 46 86 207 seg67 -35 706 46 86 208 seg68 -105 706 46 86 209 seg69 -175 706 46 86 210 seg70 -245 706 46 86 211 seg71 -315 706 46 86 212 seg72 -385 706 46 86 213 seg73 -455 706 46 86 214 seg74 -525 706 46 86 215 seg75 -595 706 46 86 216 seg76 -665 706 46 86 217 seg77 -735 706 46 86 218 seg78 -805 706 46 86 219 seg79 -875 706 46 86 220 seg80 -945 706 46 86 221 seg81 -1015 706 46 86 222 seg82 -1085 706 46 86 223 seg83 -1155 706 46 86 224 seg84 -1225 706 46 86 225 seg85 -1295 706 46 86 226 seg86 -1365 706 46 86 227 seg87 -1435 706 46 86 228 seg88 -1505 706 46 86 229 seg89 -1575 706 46 86 230 seg90 -1645 706 46 86 231 seg91 -1715 706 46 86 232 seg92 -1785 706 46 86 233 seg93 -1855 706 46 86 234 seg94 -1925 706 46 86 235 seg95 -1995 706 46 86 236 seg96 -2065 706 46 86 237 seg97 -2135 706 46 86 238 seg98 -2205 706 46 86 239 seg99 -2275 706 46 86 240 seg100 -2345 706 46 86 241 seg101 -2415 706 46 86 242 seg102 -2485 706 46 86 243 seg103 -2555 706 46 86 244 seg104 -2625 706 46 86 245 seg105 -2695 706 46 86 246 seg106 -2765 706 46 86 247 seg107 -2835 706 46 86 248 seg108 -2905 706 46 86 249 seg109 -2975 706 46 86 250 seg110 -3045 706 46 86 251 seg111 -3115 706 46 86 # name x y w h 252 seg112 -3185 706 46 86 253 seg113 -3255 706 46 86 254 seg114 -3325 706 46 86 255 seg115 -3395 706 46 86 256 seg116 -3465 706 46 86 257 seg117 -3535 706 46 86 258 seg118 -3605 706 46 86 259 seg119 -3675 706 46 86 260 seg120 -3745 706 46 86 261 seg121 -3815 706 46 86 262 seg122 -3885 706 46 86 263 seg123 -3955 706 46 86 264 seg124 -4025 706 46 86 265 seg125 -4095 706 46 86 266 seg126 -4165 706 46 86 267 seg127 -4235 706 46 86 268 seg128 -4305 706 46 86 269 seg129 -4375 706 46 86 270 seg130 -4445 706 46 86 271 seg131 -4515 706 46 86 272 seg132 -4585 706 46 86
u ltra c hip high-voltage mixed-signal ic ?1999~2003 42 product specifications t ray i nformation remark: 1.uc1606 die size :9.862*1.647*0.635mm (after wafer sawing, include scribeline dimension) 2.surface resistivity: 1*10 ~10 /cm ultra chip inc. w uc1606 ic tray type:h20-393*70-32(60) iris chen drawn 07-04-02' unit unless otherwise specified general angle dimension roughness tolerance date n/a detail drawing see by n/a mm alvin chang alvin chang 07-04-02' checked 07-04-02' approved drawing no 1 of 1 sheet size n/a package code material scale proj. a4 b rev.
uc1606 65x132 matrix lcd controller-drivers version 1.32 43 r evision h istory version contents date of rev. 1.0 first release jul. 06, 2001 1.1 frame rate increased, ac/ dc characteristics update, product naming rule added oct. 30, 2001 1.2 operation voltage up to 5.0v dec. 18, 2001 over all revision (1) recommended c l value is adjusted to 5nf ~ 20nf (page 5) (2) vdd1 is renamed to vdd (page 5) (3) tp3 is renamed to tst4 (page 7) (4) tp[2:0] is renamed to tp[3:1] (page 7) (5) c[0:131] is renamed to seg[1:132] (page 7) (6) r[1~64] is renamed to com[1~64] (page 7) (7) ric is renamed to cic (page 7) (8) application circuits are added. (page 18, 23, 24) (9) alignment mark information is presented (page 39) (10) tray information is presented. (page 43) 1.3 (11) power consumption table is presented (page 33) aug. 16, 2002 (1) the direction on dealing with unused bus pins is corrected as leaving open-circuit; instead of connecting to v dd /v ss . (section ?pin description?, page 6; ?host interface?, page 21.) (2) figures 8 and 9, reference circuit for s8/s9, are corrected to present sda=d2, instead of d3. (section ? host interface reference circuit ?, page 24) (3) ?power consumption? table is filled with data. (section ?specifications?, page 33) 1.31 (4) figures 12, 13 and 14 are patched by adding pulse cs1. (section ?ac characteristics?, pp 33-35) jun. 18, 2003
u ltra c hip high-voltage mixed-signal ic ?1999~2003 44 product specifications version contents date of rev. (1) section ?table of revision history? is renamed as ?revision history? and moved to the rear of the datasheet. (2) recommended cb value has been modified: ~ 100x ? 150 ~ 250x (section ?pin description?, page 4) (3) in the ?bits? column, number of bit is updated from ?pin? to ?2? (section ?control register s? ? ?mr? entry, page 7) (4) in the ?default? column, the default values are updated: ?00h? ? ?0h? (section ?control registers? ? en tries ?dc?, ?ac?, and ?lc?, page 8) (5) in the ?default value? column, the default value is updated: ?0011b? ? ?011b? (section ?command table? ? (5) set gain, page 9) (6) description of pc[2:1] is modified: 00b: 4x ? 01b: 4x (section ?control register?, page 9; ?command description?, page 11) (7) the description for mx is updated: mx: status of register lc[1] ? lc[2] (section ?command description? ? (3) get status, page 10) (8) in the action column, pin specifying is updated: set apc[1:0] ? apc[0] (section ?command description? ? (7) set advance product configuration, page 11) (9) the value of pins d[7:4] is corrected: 0110 ? 1011 (section ?command description? ? (9) set page address, page 11) (10) the values of wr0/wr1 of spi(s8)/spi(s9) are updated: ?-? ? ?0? (section ?host interfac e? - table 4, page 20) (11) figure 6/7: 8080/8bit and 6800/8bit para llel mode reference circuit is modified by showing rst pin. figure 8/9: serial-8/9 seri al mode reference circuit is modified as following: sda(d3) ? sda(d2) (section ?host interface refe rence circuit?, pp 22 - 23) (12) power consumption table is added . (section ?specifications?, page 32) (13) die size is updated. (section ?physical dimensions?, page 37) 1.32 (14) alignment mark information is updated. (section ?alignment mark dimension?, page 38) sep. 24, 2003

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